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rev 1.1.8 10/04/02 characteristics subject to change without notice. 1 of 30 www.xicor.com X9522 laser diode control for fiber optic modules description the X9522 combines three digitally controlled potentiome- ters (dcps), and two programmable voltage monitor inputs with software and hardware indicators. all functions of the X9522 are accessed by an industry standard 2-wire serial interface. two of the dcps of the X9522 may be utilized to control the bias and modulation currents of the laser diode in a fiber optic module. the third dcp may be used to set other vari- ous reference quantities, or as a coarse trim for one of the other two dcps.the programmable voltage monitors may be used for monitoring various module alarm levels. the features of the X9522 are ideally suited to simplifying the design of ?er optic modules. the integration of these functions into one package signi?antly reduces board area, cost and increases reliability of laser diode modules. block diagram vtrip data register command decode & control logic sda scl constat register protect logic threshold reset logic v2 vtrip vcc / v1 v3 + - 2 3 r h2 r w2 r l2 8 6 - bit nonvolatile memory r h0 r w0 r l0 wiper register r h1 r w1 r l1 counter v2ro wp v3ro 7 - bit nonvolatile memory nonvolatile memory wiper register counter wiper register counter 8 - bit 2 + - hot pluggable triple dcp, dual voltage monitors features three digitally controlled potentiometers (dcps) 64 tap - 10 k ? 100 tap - 10 k ? 256 tap - 100 k ? nonvolatile write protect function 2-wire industry standard serial interface dual voltage monitors programmable threshold voltages single supply operation 2.7 v to 5.5 v hot pluggable 20 pin packages xbga tm tssop preliminary information ?000 xicor inc., patents pending
rev 1.1.8 10/04/02 characteristics subject to change without notice. 2 of 30 www.xicor.com X9522 ?preliminary information detailed device description the X9522 combines three xicor digitally controlled potentiometer (dcp) devices, and two voltage monitors, in one package. these functions are suited to the control, support, and monitoring of various system parameters in ?er optic modules. the combination of the X9522 fucn- tionality lowers system cost, increases reliability, and reduces board space requirements using xicors unique xbga packaging. two high resolution dcps allow for the ?et-and-forget adjustment of laser driver ic parameters such as laser diode bias and modulation currents. one lower resolu- tion dcp may be used for setting sundry system parame- ters such as maximum laser output power (for eye safety requirements). the dual voltage monitor circuits continuously compare their inputs to individual trip voltages. if an input voltage exceeds its associated trip level, a hardware output (v3ro, v2ro) are allowed to go high. if the input volt- age becomes lower than its associated trip level, the cor- responding output is driven low. a corresponding binary representation of the two monitor circuit outputs (v2ro and v3ro) are also stored in latched, volatile (constat) register bits. the status of these two monitor outputs can be read out via the 2-wire serial port. xicors unique circuits allow for all internal trip voltages to be individually programmed with high accuracy. this gives the designer great ?xibility in changing system parame- ters, either at the time of manufacture, or in the ?ld. the device features a 2-wire interface and software pro- tocol allowing operation on an i 2 c compatible serial bus. pin configuration v2 r l2 r h0 3 4 vcc / v1 scl r w0 r l0 r w1 r h1 7 8 v3 v ss 10 r l1 r h2 1 18 19 17 20 14 15 13 16 12 11 nc 6 r w2 2 sda 9 v3ro 5 wp nc v2ro not to scale 20 pin tssop 2 3 4 a b c d e top view ?bumps down 1 xbga r l2 r w2 r h2 v2 wp v3ro scl r h0 sda r l1 v2ro v1 / vcc v3 nc r w0 r l0 r h1 nc v ss r w1
rev 1.1.8 10/04/02 characteristics subject to change without notice. 3 of 30 www.xicor.com X9522 ?preliminary information pin assignment pin xbga name function 1b3 r h2 connection to end of resistor array for (the 256 tap) dcp 2. 2a3 r w2 connection to terminal equivalent to the ?iper of a mechanical potentiometer for dcp 2. 3a4 r l2 connection to other end of resistor array for (the 256 tap) dcp2. 4b4v3 v3 voltage monitor input. v3 is the input to a non-inverting voltage comparator circuit. when the v3 input is higher than the v trip3 threshold voltage, v3ro makes a transition to a high level. connect v3 to v ss when not used. 5 c3 v3ro v3 reset output. this open drain output makes a transition to a high level when v3 is greater than v trip3 and goes low when v3 is less than trip3 . there is no delay circuitry on this pin. the v3ro pin requires the use of an external ?ull-up resistor. 7c4wp write protect control pin. wp pin is a ttl level compatible input. when held high, write protection is enabled. in the enabled state, this pin prevents all nonvolatile ?rite opera- tions. also, when the write protection is enabled, and the dcp write lock feature is active (i.e. the dcp write lock bit is set to ??, then no ?rite (volatile or nonvolatile) operations can be performed in the device (including the wiper position of any of the integrated digitally controlled potentiometers (dcps). the wp pin uses an internal ?ull-down resistor, thus if left ?ating the write protection feature is disabled. 8 d4 scl serial clock. this is a ttl level compatible input pin used to control the serial bus timing for data input and output. 9e4sda serial data. sda is a bidirectional ttl level compatible pin used to transfer data into and out of the device. the sda pin input buffer is always active (not gated). this pin requires an external pull up resistor. 10 e1 vss ground. 11 e3 r l1 connection to other end of resistor for (the 100 tap) dcp 1. 12 e2 r w1 connection to terminal equivalent to the ?iper of a mechanical potentiometer for dcp 1 13 d1 r h1 connection to end of resistor array for (the 100 tap) dcp 1. 14 d2 r h0 connection to end of resistor array for (the 64 tap) digitally controlled potentiometer (dcp) 0. 15 c1 r w0 connection to terminal equivalent to the ?iper of a mechanical potentiometer for dcp 0. 16 c2 r l0 connection to the other end of resistor array for (the 64 tap) dcp 0. 17 b1 v2 v2 voltage monitor input. v2 is the input to a non-inverting voltage comparator circuit. when the v2 input is greater than the v trip2 threshold voltage, v2ro makes a transition to a high level. connect v2 to v ss when not used. 18 a1 v2ro v2 reset output. this open drain output makes a transition to a high level when v2 is greater than v trip2 , and goes low when v2 is less than v trip2 . there is no power up reset delay circuitry on this pin. the v2ro pin requires the use of an external ?ull-up re- sistor. 20 a2 vcc / v1 supply voltage. 6, 19 b2, d3 nc no connect
rev 1.1.8 10/04/02 characteristics subject to change without notice. 4 of 30 www.xicor.com X9522 ?preliminary information principles of operation serial interface serial interface conventions the device supports a bidirectional bus oriented protocol. the protocol de?es any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the master always initiates data transfers, and provides the clock for both transmit and receive operations. there- fore, the X9522 operates as a slave in all applications. serial clock and data data states on the sda line can change only while scl is low. sda state changes while scl is high are reserved for indicating start and stop conditions. see figure 1.on power up of the X9522, the sda pin is in the input mode. serial start condition all commands are preceded by the start condition, which is a high to low transition of sda while scl is high. the device continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition has been met. see figure 2. serial stop condition all communications must be terminated by a stop condi- tion, which is a low to high transition of sda while scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. see figure 2. serial acknowledge an acknowledge (ack) is a software convention used to indicate a successful data transfer. the transmit- ting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowl- edge that it received the eight bits of data. refer to fig- ure 3. the device will respond with an acknowledge after recognition of a start condition if the correct device identi?r bits are contained in the slave address byte. if a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. in the read mode, the device will transmit eight bits of data, release the sda line, then monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. the device will termi- scl sda data stable data change data stable figure 1. valid data changes on the sda bus scl sda start stop figure 2. valid start and stop conditions
rev 1.1.8 10/04/02 characteristics subject to change without notice. 5 of 30 www.xicor.com X9522 ?preliminary information nate further data transmissions if an acknowledge is not detected. the master must then issue a stop condi- tion to place the device into a known state. device internal addressing addressing protocol overview the user addressable internal components of the X9522 can be split up into two main parts: ?hree digitally controlled potentiometers (dcps) ?ontrol and status (constat) register depending upon the operation to be performed on each of these individual parts, a 1, 2 or 3 byte protocol is used. all operations however must begin with the slave address byte being issued on the sda pin. the slave address selects the part of the X9522 to be addressed, and speci- ?s if a read or write operation is to be performed. it should be noted that in order to perform a write opera- tion to a dcp, the write enable latch (wel) bit must ?st be set. slave address byte following a start condition, the master must output a slave address byte (refer to figure 4.). this byte con- sists of three parts: ?he device type identi?r which consists of the most signi?ant four bits of the slave address (sa7 - sa4). the device type identi?r must always be set to 1010 in order to select the X9522. ?he next three bits (sa3 - sa1) are the internal device address bits. setting these bits to 111 internally selects the dcp structures in the X9522. the constat regis- ter may be selected using the internal device address 010.all other bit combinations are reserved. ?he least signi?ant bit of the slave address (sa0) byte is the r/w bit. this bit de?es the operation to be performed on the device being addressed (as de?ed in the bits sa3 - sa1). when the r/w bit is ?? then a read operation is selected. a ? selects a write operation (refer to figure 4.) scl from master data output from transmitter data output from receiver 8 1 9 start acknowledge figure 3. acknowledge response from receiver scl from master sa6 sa7 sa5 sa3 sa2 sa1 sa0 device type identifier read / sa4 internal address (sa3 - sa1) internally addressed device 010 constat register 111 dcp others reserved bit sa0 operation 0 write 1 read r/w figure 4. slave address format 101 0 write address internal device
rev 1.1.8 10/04/02 characteristics subject to change without notice. 6 of 30 www.xicor.com X9522 ?preliminary information nonvolatile write acknowledge polling after a nonvolatile write command sequence (for either the non volatile memory of a dcp (nvm), or the con- stat register) has been correctly issued (including the ?al stop condition), the X9522 initiates an internal high voltage write cycle. this cycle typically requires 5 ms. dur- ing this time, no further read or write commands can be issued to the device. write acknowledge polling is used to determine when this high voltage write cycle has been completed. to perform acknowledge polling, the master issues a start condition followed by a slave address byte. the slave address issued must contain a valid internal device address. the lsb of the slave address (r/w ) can be set to either 1 or 0 in this case. if the device is still busy with the high voltage cycle then no acknowledge will be returned. if the device has completed the write operation, an acknowledge will be returned and the host can then proceed with a read or write operation. (refer to fig- ure 5.). digitally controlled potentiometers dcp functionality the X9522 includes three independent resistor arrays. these arrays respectively contain 63, 99 and 255 discrete resistive segments that are connected in series. the physical ends of each array are equivalent to the ?ed terminals of a mechanical potentiometer (r hx and r lx inputs - where x = 0,1,2). at both ends of each array and between each resistor segment there is a cmos switch connected to the wiper (r w x ) output. within each individual array, only one switch may be turned on at any one time. these switches are controlled by the wiper counter register (wcr) (see figure 6). the wcr is a volatile register. on power up of the X9522, wiper position data is auto- matically loaded into the wcr from its associated non volatile memory (nvm) register. the table below shows the initial values of the dcp wcrs before the contents of the nvm is loaded into the wcr. the data in the wcr is then decoded to select and enable one of the respective fet switches. a ?ake ack returned? issue slave address byte (read or write) byte load completed by issuing stop. enter ack polling issue stop issue start no yes high voltage cycle complete. continue command sequence? issue stop no continue normal read or write command sequence proceed yes figure 5. acknowledge polling sequence decoder resistor array r hx fet switches r lx r wx 0 1 2 n wiper register counter non memory volatile (wcr) (nvm) ?iper figure 6. dcp internal structure dcp initial values before recall r 0 / 64 tap v h / tap = 63 r 1 / 100 tap v l / tap = 0 r 2 / 256 tap v h / tap = 255
rev 1.1.8 10/04/02 characteristics subject to change without notice. 7 of 30 www.xicor.com X9522 ?preliminary information before break sequence is used internally for the fet switches when the wiper is moved from one tap position to another. hot pluggability figure 7 shows a typical waveform that the X9522 might experience in a hot pluggable situation. on power up, vcc / v1 applied to the X9522 may exhibit some amount of ringing, before it settles to the required value. the device is designed such that the wiper terminal (r wx ) is recalled to the correct position (as per the last stored in the dcp nvm), when the voltage applied to vcc / v1 exceeds v trip for a time exceeding t pu. therefore, if t trans is de?ed as the time taken for vcc / v1 to settle above v trip (figure 7): then the desired wiper terminal position is recalled by (a maximum) time: t trans + t pu . it should be noted that t trans is determined by system hot plug conditions. dcp operations in total there are three operations that can be performed on any internal dcp structure: ?cp nonvolatile write ?cp volatile write ?cp read a nonvolatile write to a dcp will change the ?iper position by simultaneously writing new data to the associated wcr and nvm. therefore, the new ?iper position setting is recalled into the wcr after vcc / v1 of the X9522 is powered down and then powered back up. a volatile write operation to a dcp however, changes the ?iper position by writing new data to the associated wcr only. the contents of the associated nvm register remains unchanged. therefore, when vcc / v1 to the device is powered down then back up, the ?iper position reverts to that last position written to the dcp using a nonvolatile write operation. both volatile and nonvolatile write operations are executed using a three byte command sequence: (dcp) slave address byte, instruction byte, followed by a data byte (see figure 9) a dcp read operation allows the user to ?ead out the current ?iper position of the dcp, as stored in the associated wcr. this operation is executed using the random address read command sequence, consisting of the (dcp) slave address byte followed by an instruction byte and the slave address byte again (refer to figure 10.). instruction byte while the slave address byte is used to select the dcp devices, an instruction byte is used to determine which dcp is being addressed. the instruction byte (figure 8) is valid only when the device type identi?r and the internal device address bits of the slave address are set to 1010111. in this case, the two least signi?ant bits (i1 - i0) of the instruction byte are used to select the particular dcp (0 - 2). in the case of a write to any of the dcps (i.e. the lsb of the slave address is 0), the most signi?ant bit of the instruction byte (i7), determines the write type (wt) per- formed. if wt is ?? then a nonvolatile write to the dcp occurs. in this case, the ?iper position of the dcp is changed by simultaneously writing new data to the associated wcr figure 7. dcp power up t vcc v trip vcc (max.) t pu maximum wiper recall time 0 t trans
rev 1.1.8 10/04/02 characteristics subject to change without notice. 8 of 30 www.xicor.com X9522 ?preliminary information and nvm. therefore, the new ?iper position setting is recalled into the wcr after vcc / v1 of the X9522 has been powered down then powered back up if wt is ? then a dcp volatile write is performed. this operation changes the dcp ?iper position by writing new data to the associated wcr only. the contents of the associated nvm register remains unchanged. therefore, when vcc / v1 to the device is powered down then back up, the ?iper position reverts to that last written to the dcp using a nonvolatile write operation. dcp write operation a write to dcpx (x=0,1,2) can be performed using the three byte command sequence shown in figure 9. in order to perform a write operation on a particular dcp, the write enable latch (wel) bit of the constat regis- ter must ?st be set (see ?el: write enable latch (vola- tile) on page 10.) the slave address byte 10101110 speci?s that a write to a dcp is to be conducted. an acknowledge is returned by the X9522 after the slave address, if it has been received correctly. next, an instruction byte is issued on sda. bits p1 and p0 of the instruction byte determine which wcr is to be written, while the wt bit determines if the write is to be volatile or nonvolatile. if the instruction byte format is valid, another acknowledge is then returned by the X9522. following the instruction byte, a data byte is issued to the X9522 over sda. the data byte contents is latched into the wcr of the dcp on the ?st rising edge of the clock signal, after the lsb of the data byte (d0) has been issued on sda (see figure 25). the data byte determines the ?iper position (which fet switch of the dcp resistive array is switched on) of the dcp. the maximum value for the data byte depends upon which dcp is being addressed (see table below). using a data byte larger than the values speci?d above results in the ?iper terminal being set to the highest tap position. the ?iper position does not roll-over to the lowest tap position. for dcp0 (64 tap) and dcp2 (256 tap), the data byte maps one to one to the ?iper position of the dcp ?iper terminal? therefore, the data byte 00001111 (15 10 ) cor- responds to setting the ?iper terminal to tap position 15. similarly, the data byte 00011100 (28 10 ) corresponds to wt ? description 0 select a volatile write operation to be performed on the dcp pointed to by bits p1 and p0 1 select a nonvolatile write operation to be per- formed on the dcp pointed to by bits p1 and p0 0 0 wt 0 0 0 p1 p0 write type dcp select ? this bit has no effect when a read operation is being performed. i5 i6 i7 i4 i3 i2 i1 i0 figure 8. instruction byte format s t a r t 10101110 a c k wt 0 0 0 0 0 p1 p0 a c k s t o p a c k d7 d6 d5 d4 d3 d2 d1 d0 slave address byte instruction byte data byte figure 9. dcp write command sequence p1- p0 dcpx # taps max. data byte 0 0 x=0 64 3fh 0 1 x=1 100 refer to appendix 1 1 0 x=2 256 ffh 1 1 reserved
rev 1.1.8 10/04/02 characteristics subject to change without notice. 9 of 30 www.xicor.com X9522 ?preliminary information setting the ?iper terminal to tap position 28. the map- ping of the data byte to ?iper position data for dcp1 (100 tap), is shown in ?ppendix 1? an example of a simple c language function which ?ranslates between the tap position (decimal) and the data byte (binary) for dcp1, is given in ?ppendix 2? it should be noted that all writes to any dcp of the X9522 are random in nature. therefore, the data byte of consec- utive write operations to any dcp can differ by an arbi- trary number of bits. also, setting the bits p1=1, p0=1 is a reserved sequence, and will result in no acknowl- edge after sending an instruction byte on sda. the factory default setting of all ?iper position settings is with 00h stored in the nvm of the dcps. this corre- sponds to having the ?iper teminal r wx (x=0,1,2) at the ?owest tap position, therefore, the resistance between r wx and r lx is a minimum (essentially only the wiper resistance, r w ). dcp read operation a read of dcpx (x=0,1,2) can be performed using the three byte random read command sequence shown in figure 10. the master issues the start condition and the slave address byte 10101110 which speci?s that a ?ummy write is to be conducted. this ?ummy write operation sets which dcp is to be read (in the preceding read operation). an acknowledge is returned by the X9522 after the slave address if received correctly. next, an instruction byte is issued on sda. bits p1-p0 of the instruction byte determine which dcp ?iper position is to be read. in this case, the state of the wt bit is ?on? care? if the instruction byte format is valid, then another acknowledge is returned by the X9522. following this acknowledge, the master immediately issues another start condition and a valid slave address byte with the r/w bit set to 1. then the X9522 issues an acknowledge followed by data byte, and ?ally, the master issues a stop condition. the data byte read in this operation, corresponds to the ?iper position (value of the wcr) of the dcp pointed to by bits p1 and p0. it should be noted that when reading out the data byte for dcp0 (64 tap), the upper two most signi?ant bits are ?nknown bits. for dcp1 (100 tap), the upper most sig- ni?ant bit is an ?nknown? for dcp2 (256 tap) however, all bits of the data byte are relevant (see figure 10). control and status register the control and status (constat) register provides the user with a mechanism for changing and reading the sta- tus of various parameters of the X9522 (see figure 11). the constat register is a combination of both volatile and nonvolatile bits. the nonvolatile bits of the constat register retain their stored values even when vcc / v1 is powered down, then powered back up. the volatile bits however, will always power up to a known logic state ? (irrespective of their value at power down). a detailed description of the function of each of the constat register bits follows: slave address instruction byte a c k a c k s t a r t s t o p slave address data byte a c k s t a r t sda bus signals from the slave signals from the master figure 10. dcp read sequence ?ummy write read operation 101 111 0 0 00 00 0 w t p 1 p 0 101 111 1 0 write operation - -- msb lsb dcpx x = 0 x = 1 x = 2 ? = don? care
rev 1.1.8 10/04/02 characteristics subject to change without notice. 10 of 30 www.xicor.com X9522 ?preliminary information wel: write enable latch (volatile) the wel bit controls the write enable status of the entire X9522 device. this bit must ?st be enabled before any write operation (to dcps, or the constat register). if the wel bit is not ?st enabled, then any proceeding (volatile or nonvolatile) write operation to dcps, or the constat register, is aborted and no acknowledge is issued after a data byte. the wel bit is a volatile latch that powers up in the dis- abled, low (0) state. the wel bit is enabled / set by writ- ing 00000010 to the constat register. once enabled, the wel bit remains set to ? until either it is reset to ? (by writing 00000000 to the constat register) or until the X9522 powers down, and then up again. writes to the wel bit do not cause an internal high volt- age write cycle. therefore, the device is ready for another operation immediately after a stop condition is executed in the constat write command sequence (see figure 12). rwel: register write enable latch (volatile) the rwel bit controls the (constat) register write enable status of the X9522. therefore, in order to write to any of the bits of the constat register (except wel), the rwel bit must ?st be set to ?? the rwel bit is a volatile bit that powers up in the disabled, low (?? state. it must be noted that the rwel bit can only be set, once the wel bit has ?st been enabled (see "constat reg- ister write operation"). the rwel bit will reset itself to the default ? state, in one of two cases: ?fter a successful write operation to any bits of the constat register has been completed (see figure 12). ?hen the X9522 is powered down. dwlk: dcp write lock bit - (nonvolatile) the dcp write lock bit (dwlk) is used to inhibit a dcp write operation (changing the ?iper position?. when the dcp write lock bit of the constat register is set to ?? then the ?iper position of the dcps cannot be changed - i.e. dcp write operations cannot be conducted: the factory default setting for this bit is dwlk= 0. important note: if the write protect (wp) pin of the X9522 is active (high), then nonvolatile write operations to the dcps are inhibited, irrespective of the dcp write lock bit setting (see "wp: write protection pin"). v2os, v3os: voltage monitor status bits (volatile) bits v2os and v3os of the constat register are latched, volatile ?g bits which indicate the status of the voltage monitor reset output pins v2ro and v3ro. at power up the vxos (x=2,3) bits default to the value ?? these bits can be set to a ? by writing the appropriate value to the constat register. to provide consistency between the vxro and vxos however, the status of the vxos bits can only be set to a ? when the correspond- ing vxro output is high. once the vxos bits have been set to ?? they will be reset to ? if: ?he device is powered down, then back up, ?he corresponding vxro output becomes low. 0 wel 0 cs5 cs6 cs7 cs4 cs3 cs2 cs1 cs0 v3os v2os dwlk 0 rwel figure 11. constat register format nv note: bits belled nv are nonvolatile (see ?ontrol and status register?. bit(s) description cs7 always set to ? (reserved) v2os v2 output status ?g v3os v3 output status ?g cs4 always set to ? (reserved) dwlk sets the dcp write lock rwel register write enable latch bit wel write enable latch bit cs0 always set to ? (reserved) dwlk dcp write operation permissible 0 yes (default) 1no
rev 1.1.8 10/04/02 characteristics subject to change without notice. 11 of 30 www.xicor.com X9522 ?preliminary information constat register write operation the constat register is accessed using the slave address set to 1010010 (refer to figure 4.). following the slave address byte, access to the constat register requires an address byte which must be set to ffh. only one data byte is allowed to be written for each constat register write operation. the user must issue a stop, after sending this byte to the register, to initiate the nonvol- atile cycle that stores the dwlk bit. the X9522 will not acknowledge any data bytes written after the ?st byte is entered (refer to figure 12.). when writing to the constat register, the bits cs7, cs4 and cs0 must all be set to ?? writing any other bit sequence to bits cs7, cs4 and cs0 of the constat register is reserved. prior to writing to the constat register, the wel and rwel bits must be set using a two step process, with the whole sequence requiring 3 steps ?rite a 02h to the constat register to set the write enable latch (wel). this is a volatile operation, so there is no delay after the write. (operation preceded by a start and ended with a stop). ?rite a 06h to the constat register to set the regis- ter write enable latch (rwel) and the wel bit. this is also a volatile cycle. the zeros in the data byte are required. (operation preceded by a start and ended with a stop). ?rite a one byte value to the constat register that has all the bits set to the desired state. the constat register can be represented as 0xy0t010 in binary, where xy are the voltage monitor output status (v2os and v3os) bits, and t is the dcp write lock (dwlk) bit. this operation is proceeded by a start and ended with a stop bit. since this is a nonvolatile write cycle, it will typically take 5ms to complete. the rwel bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. if bit 2 is set to ? in this third step (0xy0 t110) then the rwel bit is set, but the dwlk bit will remain unchanged. writing a second byte to the control register is not allowed. doing so aborts the write operation and the X9522 does not return an acknowledge. for example, a sequence of writes to the device con- stat register consisting of [02h, 06h, 02h] will reset the nonvolatile (dwlk) bit in the constat register to ?? s t a r t 1010010r/w a c k 11111 1 11 a c k scl sda s t o p a c k cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 slave address byte address byte constat register data in figure 12. constat register write command sequence 0 slave address address byte a c k a c k s t a r t s t o p slave address data a c k 1 s t a r t sda bus signals from the slave signals from the master figure 13. constat register read command sequence 0 1 0 0 1 0 11 0 1 0 0 1 0 write operation ?ummy write read operation cs7 cs0
rev 1.1.8 10/04/02 characteristics subject to change without notice. 12 of 30 www.xicor.com X9522 ?preliminary information it should be noted that a write to nonvolatile bit (dwlk) of constat register will be ignored if the write protect pin of the X9522 is active (high) (see "wp: write protection pin"). constat register read operation the contents of the constat register can be read at any time by performing a random read (see figure 13). using the slave address byte set to 10100101, and an address byte of ffh. only one byte is read by each regis- ter read operation. the X9522 resets itself after the ?st byte is read. the master should supply a stop condition to be consistent with the bus protocol. after setting the wel and / or the rwel bit(s) to a ?? a constat register read operation may occur, without interrupting a proceeding constat register write opera- tion. when reading the contents of the constat register, the bits cs7, cs4 and cs0 will always return ?? data protection there are a number of levels of data protection features designed into the X9522. any write to the device ?st requires setting of the wel bit in the constat register. a write to the constat register itself, further requires the setting of the rwel bit. the dcp write lock of the device enables the user to inhibit writes to all dcps. one further level of data protection in the X9522, is incorporated in the form of the write protection pin. wp: write protection pin when the write protection (wp) pin is active (high), it disables nonvolatile write operations to the X9522. the table below ( X9522 write permission status) sum- marizes the effect of the wp pin (and dcp write lock), on the write permission status of the device. additional data protection features in addition to the preceding features, the X9522 also incorporates the following data protection functionality: ?he proper clock count and data bit sequence is required prior to the stop bit in order to start a nonvol- atile write cycle. voltage monitoring functions v2 monitoring the X9522 asserts the v2ro output high if the volt- age v2 exceeds the corresponding v trip2 threshold (see figure 14). the bit v2os in the constat regis- ter is then set to a ??(assuming that it has been set to ??after system initilization). the v2ro output may remain active high with vcc down to 1v. figure 14. voltage monitor response vx vxro 0v 0v v tripx (x = 2,3) 0 volts v trip vcc / v1 X9522 write permission status dwlk (dcp write lock bit status) wp (write protect pin status) dcp volatile write permitted dcp nonvolatile write permitted write to constat register permitted volatile bits nonvolatile bits 1 1 no no no no 0 1 yes no no no 1 0 no no yes yes 0 0 yes yes yes yes
rev 1.1.8 10/04/02 characteristics subject to change without notice. 13 of 30 www.xicor.com X9522 ?preliminary information v3 monitoring the X9522 asserts the v3ro output high if the volt- age v3 exceeds the corresponding v trip3 threshold (see figure 14). the bit v3os in the constat regis- ter is then set to a ??(assuming that it has been set to ??after system initilization). the v3ro output may remain active high with vcc down to 1v. v tripx thresholds (x=2,3) the X9522 is shipped with pre-programmed threshold (v tripx ) voltages. in applications where the required thresholds are different from the default values, or if a higher precision / tolerance is required, the X9522 trip points may be adjusted by the user, using the steps detailed below. setting a v tripx voltage (x=2,3) there are two procedures used to set the threshold voltages (v tripx ), depending if the threshold voltage to be stored is higher or lower than the present value. for example, if the present v tripx is 2.9 v and the new v tripx is 3.2 v, the new voltage can be stored directly into the v tripx cell. if however, the new setting is to be lower than the present setting, then it is necessary to ?eset?the v tripx voltage before setting the new value. 01234567 scl sda a0h 01234567 wp v p 01234567 v tripx v2, v3 figure 15. setting v tripx to a higher level (x=1,2). 09h ? sets v trip1 0dh ? sets v trip2 data byte ? 00h s t a r t ? ? all others reserved. sda a0h ? 01234567 scl 01234567 wp v p 01234567 figure 16. resetting the v tripx level (x=2,3) 0bh ? resets vtrip2 0fh ? resets vtrip3 data byte 00h ? s t a r t ? all others reserved.
rev 1.1.8 10/04/02 characteristics subject to change without notice. 14 of 30 www.xicor.com X9522 ?preliminary information setting a higher v tripx voltage (x=2,3) to set a v tripx threshold to a new voltage which is higher than the present threshold, the user must apply the desired v tripx threshold voltage to the corre- sponding input pin (v2 or v3). then, a programming voltage (vp) m ust be applied to the wp pin before a start condition is set up on sda. next, issue on the sda pin the slave address a0h, followed by the byte address 09h for v trip3 , and 0dh for v trip3 , and a 00h data byte in order to program v tripx . the stop bit following a valid write operation initiates the program- ming sequence. pin wp must then be brought low to complete the operation (see figure 16). the user does not have to set the wel bit in the constat register before performing this write sequence. setting a lower v tripx voltage (x=2,3) in order to set v tripx to a lower voltage than the present value, then v tripx must first be ?eset?accord- ing to the procedure described below. once v tripx has been ?eset? then v tripx can be set to the desired voltage using the procedure described in ?etting a higher v tripx voltage? resetting the v tripx voltage to reset a v tripx voltage, apply the programming volt- age (vp) to the wp pin bef ore a start condition is set up on sda. next, issue on the sda pin the slave address a0h followed by the byte address 0bh for v trip2 , and 0fh for v trip3 , followed by 00h for the data byte in order to reset v tripx . the stop bit fol- lowing a valid write operation initiates the programming sequence. pin wp must then be brought low to com- plete the operation (see figure 16).the user does not have to set the wel bit in the constat register before performing this write sequence. after being reset, the value of v tripx becomes a nomi- nal value of 1.7v. v tripx accuracy (x=2,3) the accuracy with which the v tripx thresholds are set, can be controlled using the iterative process shown in fig- ure 17. if the desired threshold is less that the present threshold voltage, then it must ?st be ?eset (see "resetting the vtripx voltage"). the desired threshold voltage is then applied to the appropriate input pin (v2 or v3) and the procedure described in section ?etting a higher v tripx voltage must be followed. once the desired v tripx threshold has been set, the error between the desired and (new) actual set threshold can be determined. this is achieved by applying vcc / v1 to the device, and then applying a test voltage higher than the desired threshold voltage, to the input pin of the volt- age monitor circuit whose v tripx was programmed. for example, if v trip2 was set to a desired level of 3.0 v, then a test voltage of 3.4 v may be applied to the voltage moni- tor input pin v2. in all cases, care should be taken not to exceed the maximum input voltage limits. after applying the test voltage to the voltage monitor input pin, the test voltage can be decreased (either in discrete steps, or continuously) until the output of the voltage mon- itor circuit changes state. at this point, the error between the actual / measured, and desired threshold levels is cal- culated. for example, the desired threshold for v trip2 is set to 3.0 v, and a test voltage of 3.4 v was applied to the input pin v2 (after applying power to vcc / v1). the input voltage is decreased, and found to trip the associated output level of pin v2ro from a low to a high, when v2 reaches 3.09 v. from this, it can be calculated that the programming error is 3.09 - 3.0 = 0.09 v. if the error between the desired and measured v tripx is less than the maximum desired error, then the program- ming process may be terminated. if however, the error is greater than the maximum desired error, then another iteration of the v tripx programming sequence can be performed (using the calculated error) in order to further increase the accuracy of the threshold voltage. if the calculated error is greater than zero, then the v tripx must ?st be ?eset? and then programmed to the a value equal to the previously set v tripx minus the calculated error. if it is the case that the error is less than zero, then the v tripx must be programmed to a value equal to the previously set v tripx plus the absolute value of the calcu- lated error. continuing the previous example, we see that the calcu- lated error was 0.09v. since this is greater than zero, we must ?st ?eset the v trip2 threshold, then apply a volt- age equal to the last previously programmed voltage, minus the last previously calculated error. therefore, we must apply v trip1 = 2.91 v to pin v2 and execute the programming sequence (see "setting a higher vtripx voltage (x=2,3)"). using this process, the desired accuracy for a particular v tripx threshold may be attained using a successive number of iterations.
rev 1.1.8 10/04/02 characteristics subject to change without notice. 15 of 30 www.xicor.com X9522 ?preliminary information v tripx programming apply vcc & voltage decrease vx switches? actual v tripx - desired v tripx done execute sequence v tripx reset set vx = desired v tripx execute sequence set higher v tripx new vx applied = old vx applied + | error | execute sequence reset v tripx new vx applied = old vx applied - | error | error < mde | error | < | mde | yes no error >mde + no yes figure 17. v tripx setting / reset sequence (x=1,2,3) > desired v tripx to vx desired v tripx < present value? note: x = 1,2,3. let: mde = maximum desired error output acceptable error range mde + mde error = actual ?desired = error desired value
rev 1.1.8 10/04/02 characteristics subject to change without notice. 16 of 30 www.xicor.com X9522 ?preliminary information absolute maximum ratings recommended operating conditions note: stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this speci?ation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability figure 18. equivalent a.c. circuit figure 19. dcp spice macromodel parameter min. max. units temperature under bias ?5 +135 ? storage temperature ?5 +150 ? voltage on wp pin (with respect to vss) ?.0 +15 v voltage on other pins (with respect to vss) ?.0 +7 v | voltage on r hx ?voltage on r lx | (x=0,1,2. referenced to vss ) vcc / v1 v d.c. output current (sda,v2ro,v3ro) 0 5ma lead temperature (soldering, 10 seconds) 300 ? supply voltage limits (applied vcc / v1 voltage, referenced to vss) 2.7 5.5 v temperature min. max. units commercial 070 ? industrial ?0 +85 ? vcc / v1 = 5v v2ro 100pf sda 2300 ? v3ro c h c l r wx 10pf 10pf r hx r lx r total c w 25pf r w (x=0,1,2)
rev 1.1.8 10/04/02 characteristics subject to change without notice. 17 of 30 www.xicor.com X9522 ?preliminary information timing diagrams figure 20. bus timing figure 21. wp pin timing figure 22. write cycle timing t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda in sda out t f t low t buf t a t r t hd:wp scl sda in wp t su:wp clk 1 clk 9 start scl sda t wc 8th bit of last byte ack stop condition start condition
rev 1.1.8 10/04/02 characteristics subject to change without notice. 18 of 30 www.xicor.com X9522 ?preliminary information figure 23. v2, v3 timing diagram figure 24. v tripx programming timing diagram (x=2,3) vx t rx t fx v tripx v rvalid vxro t rpdx 0 volts note : x = 2,3. 0 volts 0 volts t rpdx t rpdx t rpdx v trip vcc / v1 wp t vps v p t vpo scl sda t wc t tsu t thd v2, v3 v tripx 00h t vph note : vcc / v1 must be greater than v2, v3 when programming.
rev 1.1.8 10/04/02 characteristics subject to change without notice. 19 of 30 www.xicor.com X9522 ?preliminary information figure 25. dcp ?iper position timing s t a r t 10101110 a c k wt 0 0 0 0 0 p1 p0 a c k s t o p a c k d7 d6 d5 d4 d3 d2 d1 d0 slave address byte instruction byte data byte scl sda time rwx (x=0,1,2) t wr r wx(n+1) r wx(n-1) r wx(n) n = tap position
rev 1.1.8 10/04/02 characteristics subject to change without notice. 20 of 30 www.xicor.com X9522 ?preliminary information d.c. operating characteristics notes: 1. the device enters the active state after any start, and remains active until: 9 clock cycles later if the device select bits in the slave address byte are incorrect; 200ns after a stop ending a read operation; or t wc after a stop ending a write operation. notes: 2. the device goes into standby: 200ns after any stop, except those that initiate a high voltage write cycle; t wc after a stop that initiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct device select bits in the slave address byte. notes: 3. current through external pull up resistor not included. notes: 4. v in = voltage applied to input pin. notes: 5. v out = voltage applied to output pin. notes: 6. see ?rdering information on page 30. notes: 7. v il min. and v ih max. are for reference only and are not tested symbol parameter min typ max unit test conditions / notes i cc1 (1) current into vcc / v1 pin (X9522: active) read memory array (3) write nonvolatile memory 0.4 1.5 ma f scl = 400khz i cc2 (2) current into vcc / v1 pin (X9522:standby) with 2-wire bus activity (3) no 2-wire bus activity 50 50 a v sda = vcc / v1 wp = vss or open/floating v scl = vcc / v1 (when no bus ac- tivity else f scl = 400khz) i li input leakage current (scl, sda) 0.1 10 a v in (4) = gnd to vcc / v1 . input leakage current (wp) 10 a i ai analog input leakage 1 10 a v in = v ss to v cc with all other analog pins ?ating i lo output leakage current (sda, v2ro, v3ro) 0.1 10 a v out (5) = gnd to vcc / v1 . X9522 is in standby (2) v tripxpr v tripx programming range (x=1,2) 1.8 4.70 v v trip1 (6) pre - programmed v trip1 threshold 1.65 2.85 1.8 3.0 1.85 3.05 v factory shipped default option a factory shipped default option b v trip2 (6) pre - programmed v trip2 threshold 1.65 2.85 1.8 3.0 1.85 3.05 v factory shipped default option a factory shipped default option b i vx v2 input leakage current v3 input leakage current 1 1 a v sda =v scl =vcc / v1 others=gnd or vcc / v1 v il (7) input low voltage (scl, sda, wp) -0.5 0.8 v v ih (7) input high voltage (scl,sda, wp) 2.0 vcc / v1 +0.5 v v olx v2ro, v3ro, sda output low voltage 0.4 v i sink = 2.0ma
rev 1.1.8 10/04/02 characteristics subject to change without notice. 21 of 30 www.xicor.com X9522 ?preliminary information a.c. characteristics (see figure 20, figure 21, figure 22) a.c. test conditions nonvolatile write cycle timing capacitance (t a = 25?c, f = 1.0 mhz, vcc / v1 = 5v) notes: 1. typical values are for t a = 25?c and vcc / v1 = 5.0v notes: 2. cb = total capacitance of one bus line in pf. notes: 3. over recommended operating conditions, unless otherwise speci?d notes: 4. t wc is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used. notes: 5. this parameter is not 100% tested. symbol parameter 400khz min max units f scl scl clock frequency 0 400 khz t in (5) pulse width suppression time at inputs 50 ns t aa (5) scl low to sda data out valid 0.1 0.9 s t buf (5) time the bus free before start of new transmission 1.3 s t low clock low time 1.3 s t high clock high time 0.6 s t su:sta start condition setup time 0.6 s t hd:sta start condition hold time 0.6 s t su:dat data in setup time 100 ns t hd:dat data in hold time 0 s t su:sto stop condition setup time 0.6 s t dh (5) data output hold time 50 ns t r (5) sda and scl rise time 20 +.1cb (2) 300 ns t f (5) sda and scl fall time 20 +.1cb (2) 300 ns t su:wp wp setup time 0.6 s t hd:wp wp hold time 0 s cb (5) capacitive load for each bus line 400 pf input pulse levels 0.1vcc to 0.9vcc input rise and fall times 10ns input and output timing levels 0.5vcc output load see figure 18 symbol parameter min. typ.(1) max. units t wc (4) nonvolatile write cycle time 5 10 ms symbol parameter max units test conditions c out (5) output capacitance (sda, v2ro, v3ro) 8 pf v out = 0v c in (5) input capacitance (scl, wp) 6 pf v in = 0v
rev 1.1.8 10/04/02 characteristics subject to change without notice. 22 of 30 www.xicor.com X9522 ?preliminary information potentiometer characteristics notes: 1. power rating between the wiper terminal r wx(n) and the end terminals r hx or r lx - for any tap position n, (x=0,1,2). notes: 2. absolute linearity is utilized to determine actual wiper resistance versus, expected resistance = (r wx(n) (actual) ?r wx(n) (expected)) = ? ml maximum (x=0,1,2). notes: 3. relative linearity is a measure of the error in step size between taps = r wx(n+1) ?[ r wx(n) + ml] = 1 ml (x=0,1,2) notes: 4. 1 ml = minimum increment = r tot / (number of taps in dcp - 1). notes: 5. typical values are for t a = 25? and nominal supply voltage. notes: 6. this parameter is periodically sampled and not 100% tested. symbol parameter limits test conditions/notesmin. typ. max. units r tol end to end resistance tolerance ?0 +20 % v rhx r h terminal voltage (x=0,1,2) vss vcc / v1 v v rlx r l terminal voltage (x=0,1,2) vss vcc / v1 v p r power rating (1) (6) 10 mw r total = 10 k ? ( dcp0, dcp1) 5mw r total = 100 k ? ( dcp2) r w dcp wiper resistance 200 400 ? i w = 1ma, vcc / v1 = 5 v, v rhx = vcc / v1, v rlx = vss (x=0,1,2). 400 1200 ? i w = 1ma, vcc / v1 = 2.7 v, v rhx = vcc / v1, v rlx = vss (x=0,1,2) i w wiper current(6) 4.4 ma noise mv / sqt(hz) r total = 10 k ? ( dcp0, dcp1) mv / sqt(hz) r total = 100 k ? ( dcp2) absolute linearity (2) -1 +1 mi (4) r w(n)(actual) ?r w(n)(expected) relative linearity (3) -1 +1 mi (4) r w(n+1) ?[r w(n)+mi ] r total temperature coefficient ?00 ppm/? r total = 10 k ? ( dcp0, dcp1) ?00 ppm/? r total = 100 k ? ( dcp2) c h /c l / c w potentiometer capacitances 10/10/ 25 pf see figure 19. t wr wiper response time(6) 200 s see figure 25. v trip vcc / v1 power up dcp recall thresh- old v t pu vcc / v1 power up dcp recall delay time (6) 25 50 75 ms
rev 1.1.8 10/04/02 characteristics subject to change without notice. 23 of 30 www.xicor.com X9522 ?preliminary information v tripx (x=1,2) programming parameters (see figure 24) notes: these parameters are not 100% tested. parameter description min typ max units t vps v tripx program enable voltage setup time 10 s t vph v tripx program enable voltage hold time 10 s t tsu v tripx setup time 10 s t thd v tripx hold (stable) time 10 s t vpo v tripx program enable voltage off time (between successive adjustments) 1ms t wc v tripx write cycle time 510 ms v p programming voltage 10 15 v v ta v tripx program voltage accuracy (programmed at 25 o c.) -100 +100 mv v tv v trip program variation after programming (-40 - 85 o c). (programmed at 25 o c.) -25 +10 +25 mv
rev 1.1.8 10/04/02 characteristics subject to change without notice. 24 of 30 www.xicor.com X9522 ?preliminary information v2ro, v3ro output timing. (see figure 23) notes: 1. see figure 23 for timing diagram. notes: 2. see figure 18 for equivalent load. notes: 3. this parameter describes the lowest possible vcc / v1 level for which the outputs v2ro, and v3ro will be correct with respect t o their inputs ( v2, v3). notes: 4. the above parameters are not 100% tested. symbol description condition min. typ. max. units t rpdx (4) v2, v3 to v2ro, v3ro propaga- tion delay (respectively) 20 s t fx (4) v2, v3 fall time 20 mv/ s t rx (4) v2, v3 rise time 20 mv/ s v rvalid (4) vcc / v1 for v2ro, v3ro valid (3) . 1v
rev 1.1.8 10/04/02 characteristics subject to change without notice. 25 of 30 www.xicor.com X9522 ?preliminary information appendix 1 dcp1 (100 tap) tap position to data byte translation table tap position data byte decimal binary 0 0 0000 0000 1 1 0000 0001 . . . . . . 23 23 0001 0111 24 24 0001 1000 25 56 0011 1000 26 55 0011 0111 . . . . . . 48 33 0010 0001 49 32 0010 0000 50 64 0100 0000 51 65 0100 0001 . . . . . . 73 87 0101 0111 74 88 0101 1000 75 120 0111 1000 76 119 0111 0111 . . . . . . 98 97 0110 0001 99 96 0110 0000
rev 1.1.8 10/04/02 characteristics subject to change without notice. 26 of 30 www.xicor.com X9522 ?preliminary information appendix 2 dcp1 (100 tap) tap position to data byte translation algorithm example. (example 1) unsigned dcp1_tap_position(int tap_pos) { int block; int i; int offset; int wcr_val; offset= 0; block = tap_pos / 25; if (block < 0) return ((unsigned)0); else if (block <= 3) { switch(block) { case (0): return ((unsigned)tap_pos) ; case (1): { wcr_val = 56; offset = tap_pos - 25; for (i=0; i<= offset; i++) wcr_val-- ; return ((unsigned)++wcr_val); } case (2): { wcr_val = 64; offset = tap_pos - 50; for (i=0; i<= offset; i++) wcr_val++ ; return ((unsigned)--wcr_val); } case (3): { wcr_val = 120; offset = tap_pos - 75; for (i=0; i<= offset; i++) wcr_val-- ; return ((unsigned)++wcr_val); } } } return((unsigned)01100000); }
rev 1.1.8 10/04/02 characteristics subject to change without notice. 27 of 30 www.xicor.com X9522 ?preliminary information appendix 2 dcp1 (100 tap) tap position to data byte translation algorithm example. (example 2) unsigned dcp100_tap_position(int tap_pos) { /* optional range checking */ if (tap_pos < 0) return ((unsigned)0); /* set to min val */ else if (tap_pos >99) return ((unsigned) 96); /* set to max val */ /* 100 tap dcp encoding formula */ if (tap_pos > 74) return ((unsigned) (195 - tap_pos)); else if (tap_pos > 49) return ((unsigned) (14 + tap_pos)); else if (tap_pos > 24) return ((unsigned) (81 - tap_pos)); else return (tap_pos); }
rev 1.1.8 10/04/02 characteristics subject to change without notice. 28 of 30 www.xicor.com X9522 ?preliminary information 20 ball bga (X9522) a b a d c e 1234 b a d c e 1 2 3 4 b top view (bump side down) side view (bump side down) bottom view (bump side up) c d e f k a j b note: drawing not to scale = die orientation mark symbol millimeters inches min nom max min nom max package body dimension x a 2.524 2.554 2.584 0.09938 0.10056 0.10174 package body dimension y b 3.794 3.824 3.854 0.14938 0.15056 0.15174 package height c 0.654 0.682 0.710 0.02575 0.02685 0.02795 body thickness d 0.444 0.457 0.470 0.01748 0.01799 0.01850 ball height e 0.210 0.225 0.240 0.00827 0.00886 0.00945 ball diameter f 0.316 0.326 0.336 0.01244 0.01283 0.01323 ball pitch ?x axis j 0.5 0.01969 ball pitch ?y axis k 0.5 0.01969 ball to edge spacing ? distance along x l 0.497 0.527 0.557 0.01957 0.02075 0.02193 ball to edge spacing ? distance along y m 0.882 0.912 0.942 0.03473 0.03591 0.03709 l m ball matrix 4321 a rl2 rw2 v1/vcc v2ro b v3 rh2 nc v2 c wp v3ro rlo rwo d scl nc rh0 rh1 e sda rl1 rw1 vss
rev 1.1.8 10/04/02 characteristics subject to change without notice. 29 of 30 www.xicor.com X9522 ?preliminary information note: all dimensions in inches (in parentheses in millimeters) 20-lead plastic, tssop package type v .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .252 (6.4) .260 (6.6) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) see detail ? .031 (.80) .041 (1.05) 0 ?8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) (4.16) (7.72) (1.78) (0.42) (0.65) all measurements are typical
rev 1.1.8 10/04/02 characteristics subject to change without notice. 30 of 30 www.xicor.com X9522 ?preliminary information ordering information device preset (factory shipped) v tripx threshold levels (x=2,3) a = optimized for 3.3 v system monitoring ? b = optimized for 5 v system monitoring ? temperature range i = industrial ?0 c to +85 c package v20 = 20-lead tssop b20 = 20-lead xbga X9522 p t xbga part mark convention 20 lead xbga top mark X9522b20i-a xacm X9522b20i-b xacn limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue produ ction and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. trademark disclaimer xicor and the xicor logo are registered trademarks of xicor, inc. autostore, direct write, block lock, serialflash, mps, and xd cp are also trademarks of xicor, inc. all others belong to their respective owners. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023, 694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents a nd additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. - y ? for details of preset threshold values , see "d.c. operating characteristics"

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